Semiconductor Reliability Engineering


"Semiconductor Reliability Engineering" refers to the development of technology, processes, and standards to ensure the reliability of semiconductor devices during application. It encompasses a vast set of engineering disciplines that ensure the continuous improvement in the reliability of every device.


Reliability is defined as the ability of a device to conform to its electrical and visual/mechanical specifications over a specified period of time under specified conditions at a specified confidence level.  Reliability engineering employs a wide variety of reliability tests (see menu on the left for descriptions of some reliability tests) to achieve continuous reliability improvement throughout the entire life cycle of the semiconductor device -  from design,  to manufacturing, to its usage, and until after its failure. 


Since it is often more difficult to improve the reliability of a semiconductor device after it has been released, as much effort as possible must be exerted to design units that are inherently reliable.  This concept is known as "Designing for Reliability", or DFR.  This consists of following all known design rules for making a device reliable, not only electrically, but visually and mechanically as well. These design rules must be updated regularly, to reflect the best known practices that ensure maximum reliability for a device.  Building reliability into a device as early as the 'design phase' is a 'must', especially now that semiconductor devices reach obsolescence more quickly than in previous years.


Once an integrated circuit has been designed and the first silicon comes out, reliability tests at wafer level are done to assess the reliability of the die.  This is known as wafer-level reliability testing.  Any reliability issues identified at this level must be corrected, since these will surely manifest even at package level. Note that the possibility of encountering wafer-level problems will be greatly minimized by diligently following the concept of DFR. 


If the new circuit passes wafer-level reliability testing, the wafer is assembled into its intended package.  The packaged device will then undergo package-level reliability testing.


Package-level reliability testing refers to the assessment of the over-all reliability of the device in packaged form.  This consists of subjecting packaged samples to reliability tests that expose the various sample sets to different stress conditions, after which the samples are tested for any degradation in quality after the stress.  Since reliability stresses are often destructive, only a sample population is used for reliability testing.  As such, the assessment of the reliability of the rest of the population is essentially statistical and probabilistic in nature.


There are many industry-standard package-level reliability tests already available.  The reliability test employed is chosen based on the failure mechanism of interest to the engineer, as different stress tests accelerate different failure mechanisms.  Nonetheless, most reliability tests utilize one or more of the following stress factors to accelerate failure: temperature, moisture or humidity, current, voltage, and pressure. The most popular industry-standard reliability tests for semiconductors are shown in the menu on the left.


Prior to the official release of a new device for mass manufacturing, it must undergo full qualification.  New device qualification is operationally the same as package-level reliability testing, except that it is systematized with the objective of generating official reliability data that would justify the mass manufacturing of the new device.  New device qualification most often requires several sets of samples for different reliability tests.


Once the final semiconductor device has successfully completed the qualification process, it may be released for mass manufacturing and consumption.  To ensure that no major process deviations occur in the manufacturing line, a regular monitoring of the reliability of the manufactured units is performed.  Reliability monitoring, as this activity is often referred to, consists of getting finished samples from the line and subjecting these to reliability testing.  Valid reliability failures should undergo root cause analysis for reliability improvement.


In summary, an excellent semiconductor reliability engineering system would have all of the following components: 1)  design for reliability; 2) wafer-level reliability testing; 3) package-level reliability testing; 4) new device/process qualification; and 5) reliability monitoring.


Reliability Tests:   Autoclave Test or PCT Temperature Cycling Thermal Shock THB HAST HTOL LTOL HTSSolder Heat Resistance Test (SHRT) Other Reliability Tests


See Also:   MIL-STD-883 Methods;  JEDEC Standards;   Life Distribution Functions Reliability Modeling Qualification Process Failure Analysis





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