Common Test/Operating Parameters for EPROM's

   

Table 1.  Common Read Operation Parameters for UV-Erasable

Programmable Read Only  Memories (EPROM's)

Test Parameter

Unit

Typical Description

Operating Current,

Read Mode

mA

This is the maximum amount of current that an EPROM in data read mode consumes while the chip is selected and the outputs are enabled.

Standby Current

mA

This is the maximum amount of current that the EPROM consumes while it is deselected, i.e., while the chip select pin is disabled.

Input Load Current

A

This is the maximum amount of current flowing through an input pin with the input voltage set to a specified voltage.

Output Leakage Current

A

This is the maximum amount of current flowing through an output pin when the chip is deselected.

Logic Input High Voltage, VIH (Logic "1")

V

This is the minimum voltage that the I/O pins of the EPROM are guaranteed to recognize as a Logic "1".

 Example of an Actual Spec: 2.0 V min.

Logic Input Low Voltage, VIL (Logic "0")

V

This is the maximum voltage that the I/O pins of the EPROM are guaranteed to recognize as a Logic "0".

Example of an Actual Spec: 0.8 V max.

Logic Output High Voltage, VOH (Logic "1")

V

This is the minimum voltage that the I/O pins of the EPROM are guaranteed to output as a Logic "1".

 Example of an Actual Spec: 2.4 V min.

Logic Output Low Voltage, VOL (Logic "0")

V

This is the maximum voltage that the I/O pins of the EPROM are guaranteed to output as a Logic "0".

Example of an Actual Spec: 0.4 V max.

Vpp Read Voltage

V

This is the voltage range acceptable to the Vpp pin when the EPROM is in read mode.

Vpp Read Current, Ipp

mA

This is the maximum current that the Vpp pin consumes when it is set to a specified voltage while the EPROM is in read mode.

Access Time (or Address to Output Delay)

nsec

This is the maximum amount of time delay for the output data to become valid after the address has become valid.

Chip Enable to Output Delay

nsec

This is the maximum amount of time delay for the output data to become valid after the chip has been enabled, i.e., the chip enable pin has been activated.

Output Enable to Output Delay

nsec

This is the maximum amount of time delay for the output data to become valid after the output pins have been enabled, i.e., the output enable pin has been activated.

Output Disable to Output Float Delay

nsec

This is the maximum amount of time delay for the outputs to be in high impedance mode after the output enable pin has been deactivated.

                               

Table 2.  Common Programming Parameters for Erasable

Programmable Read Only  Memories (EPROM's)

Test Parameter

Unit

Typical Description

Operating Current,

Program Mode

mA

This is the maximum amount of current consumed by the EPROM for programming and data verification.

Vpp Programming Voltage

V

This is the voltage range acceptable to the Vpp pin when the EPROM is in program mode.

Vcc Programming Voltage

V

This is the voltage range acceptable to the Vcc pin when the EPROM is in program mode.

Logic Input High Voltage, VIH (Logic "1")

V

This is the minimum voltage that the I/O pins of the EPROM are guaranteed to recognize as a Logic "1".

 Example of an Actual Spec: 2.0 V min.

Logic Input Low Voltage, VIL (Logic "0")

V

This is the maximum voltage that the I/O pins of the EPROM are guaranteed to recognize as a Logic "0".

Example of an Actual Spec: 0.8 V max.

Logic Output High Voltage, VOH (Logic "1")

V

This is the minimum voltage that the I/O pins of the EPROM are guaranteed to output as a Logic "1".

 Example of an Actual Spec: 2.4 V min.

Logic Output Low Voltage, VOL (Logic "0")

V

This is the maximum voltage that the I/O pins of the EPROM are guaranteed to output as a Logic "0".

Example of an Actual Spec: 0.4 V max.

Address Set-up Time

nsec

This is the minimum amount of time that the address must be valid before the program pin is enabled to read the data into the program.

Data Set-up Time

nsec

This is the minimum amount of time that the data to be programmed must be valid before the program pin is enabled to read the data into the program.

Output Enable Setup Time

nsec

The I/O pins of an EPROM are in high impedance mode if they are not being used as inputs for programming (output disabled) or as outputs for data verification (output enabled). The output enable set-up time is the minimum amount of time needed for the outputs to be in this high impedance mode before they are enabled for data verification.

Address Hold Time

nsec

This is the minimum amount of time needed before a new address is provided after the I/O pins have been set up as input pins for programming of new data. The I/O pins become inputs when the output enable pin is deactivated.

Data Hold Time

nsec

This is the minimum amount of time that the output data (for data verification) will be valid after the outputs have been disabled, i.e., the I/O pins are changed into input pins.

Vpp Set-up Time

nsec

This is the minimum amount of time that the Vpp voltage must be stable before the program pin is enabled to read in the data for programming.

Vcc Set-up Time

nsec

This is the minimum amount of time that the Vcc voltage must be stable before the program pin is enabled to read in the data for programming.

Program Pulse Width

nsec

This specifies the minimum and maximum time acceptable as pulse width for the pulse input to the program pin when programming data into the EPROM.

Data Valid from Output Enable

nsec

This is the minimum amount of time needed for the output data (during data verification) to become valid after the output enable pin has been activated.

     

 

 

See Also:  EPROMs Electrical Test

  

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