Common Test/Operating Parameters for SRAM's  

   

Test Parameter

Unit

Typical Description

Operating Current

mA

This is the maximum amount of current that the SRAM consumes while it is in operation with the Vcc at maximum, the chip select pin active, and the outputs in high impedance.

Standby Current

mA

This is the maximum amount of current that the SRAM consumes while it is deselected, i.e., while the chip select pin is disabled.

Output Leakage Current

A

This is the maximum amount of current flowing through an I/O pin when the chip is deselected.

Logic Input High Voltage, VIH (Logic "1")

V

This is the minimum voltage that the I/O pins of the SRAM are guaranteed to recognize as a Logic "1".

 Example of an Actual Spec: 2.0 V min.

Logic Input Low Voltage, VIL (Logic "0")

V

This is the maximum voltage that the I/O pins of the SRAM are guaranteed to recognize as a Logic "0".

Example of an Actual Spec: 0.8 V max.

Logic Output High Voltage, VOH (Logic "1")

V

This is the minimum voltage that the I/O pins of the SRAM are guaranteed to output as a Logic "1".

 Example of an Actual Spec: 2.4 V min.

Logic Output Low Voltage, VOL (Logic "0")

V

This is the maximum voltage that the I/O pins of the SRAM are guaranteed to output as a Logic "0".

Example of an Actual Spec: 0.4 V max.

Read Cycle Time

nsec

This is the minimum amount of time needed to complete one read cycle from one memory address to another.

Address Access Time

nsec

This is the maximum amount of time needed for the data read from a memory address to become valid as referenced from the time the address becomes valid.

Chip Select Access Time

nsec

This is the maximum amount of time needed for the data read from a memory address to become valid as referenced from the time the chip select pin is enabled.

Output Hold from Address Change Time

nsec

This is the minimum amount of time that the data from the previous memory address will be valid as referenced from the time the new address becomes valid.

Chip Selection to Active Output Time

nsec

This is the minimum amount of time needed for the output lines to start becoming active from the time the chip is selected.

Chip Deselection to High Impedance Output Time

nsec

This is the maximum amount of time needed to put the output lines in high impedance mode from the time the chip is deselected.

Write Cycle Time

nsec

This is the minimum amount of time needed to complete one write cycle from one memory address to another.

Chip Select to End of Write Time

nsec

This is the minimum amount of time needed that the write enable pin must be active for a successful write cycle as referenced from the time the chip select pin is enabled.

Address Valid to End of Write Time

nsec

This is the minimum amount of time needed that the write enable pin must be active for a successful write cycle as referenced from the time the address becomes valid.

Address Set-up Time

nsec

This is the minimum amount of time needed before the write enable pin is activated from the time the address becomes valid.

Write Pulse Width

nsec

This is the minimum amount of time that the write enable pin must be in active mode for the write cycle to be successful.

Write Recovery Time

nsec

This is the minimum amount of time needed from the time the write enable pin is deactivated before a new write address is provided.

Data Valid to End of Write Time

nsec

This is the minimum amount of time that the written data must be valid before the write enable pin is deactivated.

Data Hold Time

nsec

This is the minimum amount of time needed before new data to be written are provided at the I/O lines after the write enable pin is deactivated.

Write Enabled to High Output Impedance Time

nsec

This is the maximum amount of time it would take the I/O pins to go from output active to high impedance mode in preparation for writing data after the write enable pin is activated.

Output Active from End of Write Time

nsec

This is the minimum amount of time it would take the I/O pins to go into output mode again after the write enable pin is deactivated.

     

 

 

See Also:  SRAMs Electrical Test

             

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